Today's ultra-deep sub-micron very large scale integration (VLSI) circuit designs are extremely complex, and are characterized by escalating gate counts, shrinking wire widths, and bigger die size. The higher gate count leads to worsening on-chip average and peak current demand, while smaller wire widths directly contribute to higher power grid (PG) mesh resistance. The combination of higher peak current demand and higher PG grid resistance degrades on-chip IR (i.e., current*resistance) drop and makes Power Delivery Network (PDN) signoff a complicated and challenging task. PDN analysis and verification has emerged as a key component in modern power sign-off methodology.
Industry-standard methods for analyzing overall PDN robustness and quality include Dynamic Voltage Drop Analysis based on instantaneous current demand, as well as Static IR Analysis based on average power. Both of these techniques have become an integral part of strategies for power signoff in today's System-on-a-chip (SoC) designs. The effectiveness of these methods lies mostly in being able to run them during early stages of a physical design cycle (e.g., a floorplan stage), when power grid design changes are easier to adopt and implement.
Dynamic Voltage Drop Analysis is a technique that can provide a software-accurate voltage drop for each instance on a die, based on instantaneous current demand due to switching activity in a real application. However, there is limited availability of representative current demand profiles that can model the numerous applications for SoC devices. Dynamic Voltage Drop Analysis is also time consuming, complicated, and a cumbersome effort that often entails elaborate and error-prone setup, large analysis runtimes, and complicated post-processing of results. Thus, Dynamic Voltage Drop Analysis often does not provide timely feedback to a circuit designer about the robustness and quality of the PDN during the early physical design stages.
Static IR Analysis based on average power is another of the industry-standard methods. This technique provides quick feedback to the circuit designer, primarily for two reasons. First, the circuit designer has a fairly good estimate of worst case average power consumption and second, the leading Electronic Design Automation (EDA) tools for PDN analysis have fast and accurate Static IR drop solver engines. The result is that Static IR Analysis based on average power provides a fairly fast and accurate estimation of on-chip Static IR drop distribution. Though testing using Static IR Analysis based on average power is easy to setup and can generate quick feedback in a reasonable amount of time, the power distribution used is based on average power, which does not account for changes in on-chip power distribution as a function of time. Thus, Static IR Analysis based on average power cannot determine if a power grid is robust enough to withstand peak current demand. Relying solely on average power-based Static IR Analysis based on average power results to assess PDN bottlenecks early in the design process can provide unexpected detrimental results.
Accordingly, there are long-felt industry needs for methods and apparatus that improve upon conventional methods and apparatus, including methods and apparatus for Enhanced Static IR Drop Analysis.